1. Field of the Invention
The present invention relates in general to the field of information handling system CPU performance analysis, and more particularly to a system and method for analyzing CPU performance from a serial link front side bus.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems that manage complex tasks, such as servers, are often configured with multiple central processing units (CPUs) that cooperate to process information. Firmware loaded on a chipset within the information handling system coordinates power-up of the CPUs to load and run one or more operating systems so that the CPUs share resources loaded on the information handling system, such as memory using Non-uniform Memory Access (NUMA). During the design of NUMA multi-processor systems, engineers attempt to confirm that firmware has correctly brought the processors to an operational state by tracing the performance of firmware instructions by the processors. For example, with some systems engineers interface external equipment to the front side bus (FSB) of the CPUs to read analog signals output at the FSB. However, NUMA multi-processor systems communicate along the FSB using a serial link, such as the Hyper Transport (HT) link. Design of a CPU bus protocol analyzer that interfaces with a planar presents a complex and expensive task and, especially with multi-processor socket systems, does not offer a helpful tool for the development and debugging of firmware and hardware. For example, full speed operation of the CPUs may not be available with such an analyzer.
One difficulty with debugging multi-processor information handling systems is that some chipset settings require a system reset to take effect. Since all processors generally execute the same code path after a system reset, identifying a processor associated with a fault is particularly difficult where the fault occurs before system memory is fully configured. Available hardware tools, such as In-Circuit Emulator (ICE) available from America Arium, provide some assistance with firmware code development and debugging capability, however, such tools typically lack a processor trace capability. The lack of a processor trace capability makes identification of a fault difficult since the fault can arise from any one of plural processors that are running the same code.